Integrated circuits are formed on a semiconductor substrate, which is typically composed of silicon. Such formation of integrated circuits involves sequentially forming or depositing multiple electrically conductive and insulative layers in or on the substrate. Chemical vapor deposition (CVD) processes are widely used to form layers of materials on a semiconductor wafer. CVD processes include thermal deposition processes, in which a gas is reacted with the heated surface of a semiconductor wafer substrate, as well as plasma-enhanced CVD processes, in which a gas is subjected to electromagnetic energy in order to transform the gas into a more reactive plasma. Forming a plasma can lower the temperature required to deposit a layer on the wafer substrate, to increase the rate of layer deposition, or both.
After the material layers are formed on the wafer substrate, etching processes may be used to form geometric patterns in the layers or vias for electrical contact between the layers. Etching processes include “wet” etching, in which one or more chemical reagents are brought into direct contact with the substrate, and “dry” etching, such as plasma etching. Various types of plasma etching processes are known in the art, including plasma etching, reactive ion (RI) etching and reactive ion beam etching. In each of these plasma processes, a gas is first introduced into a reaction chamber and then plasma is generated from the gas. This is accomplished by dissociation of the gas into ions, free radicals and electrons by using an RF (radio frequency) generator, which includes one or more electrodes. The electrons are accelerated in an electric field generated by the electrodes, and the energized electrons strike gas molecules to form additional ions, free radicals and electrons, which strike additional gas molecules, and the plasma eventually becomes self-sustaining. The ions, free radicals and electrons in the plasma react chemically with the layer material on the semiconductor wafer to form residual products which leave the wafer surface and thus, etch the material from the wafer.
Referring to the schematic of FIG. 1, a wafer processing system, such as an etcher or CVD chamber, is generally indicated by reference numeral 10. The processing system 10 includes a reaction chamber 12 having a typically grounded chamber wall 14 closed by a chamber top 18. Source gases for wafer processing are provided by a gas supply 20. The gas supply 20 is coupled with the reaction chamber 12 through a gas control panel 22, which selects and controls the flow of the source gases into the reaction chamber 12. A semiconductor wafer 34 is supported on a wafer chuck 36 in the reaction chamber 12. Volatile reaction products and unreacted plasma or gas species are removed from the reaction chamber 12 by a gas removal mechanism, such as a vacuum pump 24 through a throttle valve 26.
The reaction chamber 12 may be a plasma etching chamber, in which the plasma formed in the chamber 12 includes high-energy ions, free radicals and electrons which react chemically with the surface material of the semiconductor wafer 34 to form reaction products that leave the surface of the wafer 34, thereby etching a geometrical pattern or a via in a wafer layer. The reaction chamber 12 may be a CVD chamber, in which gases are introduced into the reaction chamber 12 and a plasma may be formed from the gases in the reaction chamber 12. In a heterogenous, or surface-catalyzed reaction, the gas or plasma deposits a solid film on the surface of the wafer 34.
By regulating the flow of gases from the interior of the reaction chamber 12 to the vacuum pump 24, the throttle valve 26 of the system 10 is typically used to control the interior pressures of the reaction chamber 12. A cross-sectional view of a conventional butterfly-type throttle valve 26 is shown in FIG. 2. The conventional butterfly-type throttle valve 26 includes a cylindrical valve wall 27, in which is pivotally mounted a vane 28 at a pivot point 29. Upon flow of gases 30 from the reaction chamber 12 to the vacuum pump 26, the vane 28 pivots from the position indicated by the solid lines to the position indicated by the dashed lines, thereby regulating the flow rate of the gas from the reaction chamber 12, and thus, the interior pressure of the reaction chamber 12.
As shown in FIG. 3, an alternative conventional gate-type throttle valve 38 includes a cylindrical valve wall 39 having a vane 40 slidably mounted through a slot (not shown) in the valve wall 39 and pivotally mounted to the valve wall 39 at a pivot point 41. The vane 40 pivots to the open position shown in FIG. 3 from a closed position inside the valve interior 42 of the throttle valve 38 to establish flow of the gases from the reaction chamber 12 to the vacuum pump 24. The vane 40 partially blocks the valve interior 42 to prevent unimpeded flow of the gases, thereby regulating the flow rate of the gases through the throttle valve 38, and thus, the pressure of the gases in the reaction chamber 12.
One of the limitations inherent in the conventional single-unit throttle valves is that the valves are characterized by an inordinately long response time upon initial flow of gases into the reaction chamber in order to establish the desired pressure for the etching or CVD process. The valves are incapable of achieving both pressure accuracy and pressure stabilization at the desired value in a short period of time. Consequently, the gases flowing through the processing system from the time of initial gas flow onset until stabilization of the gas flow rate and interior chamber gas pressure, tend to be wasted. Accordingly, a new and improved, multi-phase pressure control valve, characterized by quick response or pressure stabilization time as well as pressure accuracy, is needed for semiconductor processing systems.
An object of the present invention is to provide a new and improved, multi-phase pressure control valve for process chambers used in the fabrication of semiconductors.
Another object of the present invention is to provide a new and improved, multi-phase pressure control valve for the quick and accurate stabilization of pressure in a process chamber.
Still another object of the present invention is to provide a new and improved, multi-phase pressure control valve which may be used in a variety of process chambers for semiconductor fabrication.
Yet another object of the present invention is to provide a new and improved, multi-phase pressure control valve which is particularly well-suited for use in etching chambers and CVD (chemical vapor deposition) chambers for semiconductor fabrication.
A still further object of the present invention is to provide a multi-phase pressure control valve which includes at least two control units for the quick and accurate establishment and stabilization of a desired pressure in a process chamber.
Yet another object of the present invention is to provide a multi-phase pressure control valve which may be readily installed in conventional semiconductor processing systems.
A still further object of the present invention is to provide a butterfly-type, multi-phase pressure control valve which may include outer and inner vanes for independently controlling flow of gases from a process chamber to a vacuum pump in order to facilitate quick and accurate attainment and stabilization of a desired interior chamber pressure for a semiconductor fabrication process chamber.
Another object of the present invention is to provide a gate-type multi-phase pressure control valve which may include a pivoting outer vane and an inner vane slidably disposed with respect to the outer vane for exposing a central gas flow opening in the outer vane, which outer and inner vanes independently facilitate flow of gases through the valve in order to quickly and precisely stabilize gas pressures in a semiconductor fabrication process chamber.
Still another object of the present invention is to provide a process-oriented design for a multi-phase pressure control valve.